The present invention relates to a line of manufacturing of integrated circuits containing, in particular bipolar and complementary MOS (CMOS) components. This type of line is usually called a BICMOS line.
An object of the present invention is to provide a BICMOS line wherein the dimensions of an element patterned on a mask can be lower than 0.4 xcexcm, for example, 0.2 to 0.35 xcexcm.
A more specific object of the present invention is to provide such a line wherein capacitors of high value are also forrned.
To achieve these and other objects, the present invention provides a method of manufacturing of a capacitor in a BICMOS integrated circuit manufacturing technology, including the following steps:
depositing, on a thick oxide region, a polysilicon layer corresponding to a MOS transistor gate electrode,
successively depositing a base polysilicon layer and a silicon oxide layer,
forming an opening in these last two layers,
performing a thermal anneal in an oxidizing atmosphere, to form an oxide layer,
depositing a silicon nitride layer and a spacer polysilicon layer, the width of the opening being small enough for the spacer polysilicon to completely fill up the opening after etching,
depositing an emitter polysilicon layer, and
making a contact with the base polysilicon layer and a contact with the emitter polysilicon layer.
According to an embodiment of the present invention, the thermal oxide layer has a thickness on the order of 10 nm.
According to an embodiment of the present invention, the silicon nitride layer has a thickness on the order of 30 nm.
According to an embodiment of the present invention, the gate and base polysilicon layers are P-type doped and the spacer and emitter polysilicon layers are N-type doped.
The foregoing objects, characteristics and advantages of the present invention will be discussed in detail in the following non-limiting description of specific embodiments, in connection with the accompanying drawings.